//=============================================================================
//
//Module Name:					axi_slave_if.sv
//Department:					Xidian University
//Function Description:	        AXI总线从设备Instruction Fetch
//
//------------------------------------------------------------------------------
//
//Version 	Design		Coding		Simulata	  Review		Rel data
//V1.0		Verdvana	Verdvana	Verdvana		  			2020-3-19
//
//------------------------------------------------------------------------------
//
//Version	Modified History
//V1.0		将sram控制器连接到AXI总线;
//          生成sram控制信号：sram地址，rd / wr操作和片选信号等。
//
//=============================================================================

`timescale 1ns/1ns

module axi_slave_if#(
    parameter   DATA_WIDTH  = 64,             //数据位宽
                ADDR_WIDTH  = 32,               //地址位宽              
                ID_WIDTH    = 1,               //ID位宽
                USER_WIDTH  = 1,             //USER位宽
                STRB_WIDTH  = (DATA_WIDTH/8)    //STRB位宽
)(
    /********* 时钟&复位 *********/
	input                       ACLK,
	input      	                ARESETn,
	/******** AXI总线信号 ********/
    //写地址通道
	input      [ID_WIDTH-1:0]   AWID,
	input	   [ADDR_WIDTH-1:0] AWADDR,
	input	   [7:0]            AWLEN,
	input	   [2:0]            AWSIZE,
	input	   [1:0]	        AWBURST,
//	input	  	                AWLOCK,
//	input	   [3:0]	        AWCACHE,
//	input	   [2:0]	        AWPROT,
//	input	   [3:0]	        AWQOS,
//	input	   [3:0]            AWREGION,
//	input	   [USER_WIDTH-1:0]	AWUSER,
	input	 	                AWVALID,
	output    	                AWREADY,
	//写数据通道                
//	input	   [ID_WIDTH-1:0]   WID,
	input	   [DATA_WIDTH-1:0] WDATA,
	input	   [STRB_WIDTH-1:0] WSTRB,
	input		                WLAST,
//	input	   [USER_WIDTH-1:0]	WUSER,
	input	  	                WVALID,
	output    	                WREADY,
	//写响应通道                
	output     [ID_WIDTH-1:0]   BID,
	output     [1:0]            BRESP,
//	output     [USER_WIDTH-1:0]	BUSER,
	output    	                BVALID,
	input	  	                BREADY,
	//读地址地址                
	input	   [ID_WIDTH-1:0]   ARID,
	input	   [ADDR_WIDTH-1:0] ARADDR,
	input	   [7:0]            ARLEN,
	input	   [2:0]	        ARSIZE,
	input	   [1:0]	        ARBURST,
//	input	  	                ARLOCK,
//	input	   [3:0]	        ARCACHE,
//	input	   [2:0]            ARPROT,
//	input	   [3:0]	        ARQOS,
//	input	   [3:0]	        ARREGION,
//	input	   [USER_WIDTH-1:0]	ARUSER,
	input	  	                ARVALID,
	output    	                ARREADY,
	//读数据通道                
	output     [ID_WIDTH-1:0]	RID,
	output     [DATA_WIDTH-1:0]	RDATA,
	output     [1:0]	        RRESP,
	output    	                RLAST,
//	output     [USER_WIDTH-1:0] RUSER,
	output                      RVALID,
	input	 	                RREADY,
    /********* SRAM信号 *********/
	//数据输入
	input   [63:0]	        sram_rdata,
	/********** 输出信号 **********/
	output 					ren,
	output  [3:0]			arsize,
	output  [31:0]			araddr,

    output 					wen,
	output  [3:0]			awsize,
	output  [31:0]			awaddr,
	output  [63:0]			wdata
);  

    //=========================================================
    //常量定义
    parameter   TCO     =   1;  //寄存器延时

    //=========================================================
    //写通道例化
    axi_w_channel#(
		.DATA_WIDTH(DATA_WIDTH),
		.ADDR_WIDTH(ADDR_WIDTH),
		.ID_WIDTH(ID_WIDTH),
		.USER_WIDTH(USER_WIDTH),
		.STRB_WIDTH(DATA_WIDTH/8)
	)u_axi_w_channel(
		    /********* 时钟&复位 *********/
	.ACLK				(ACLK),
	.ARESETn			(ARESETn),
	/******** AXI总线信号 ********/
    //写地址通道
	.AWID				(AWID),
	.AWADDR				(AWADDR),
	.AWLEN				(AWLEN),
	.AWSIZE				(AWSIZE),
	.AWBURST			(AWBURST),
//	input	  	                AWLOCK,
//	input	   [3:0]	        AWCACHE,
//	input	   [2:0]	        AWPROT,
//	input	   [3:0]	        AWQOS,
//	input	   [3:0]            AWREGION,
//	input	   [USER_WIDTH-1:0]	AWUSER,
	.AWVALID			(AWVALID),
	.AWREADY			(AWREADY),
	//写数据通道                
//	input	   [ID_WIDTH-1:0]   WID,
	.WDATA				(WDATA),
	.WSTRB				(WSTRB),
	.WLAST				(WLAST),
//	input	   [USER_WIDTH-1:0]	WUSER,
	.WVALID				(WVALID),
	.WREADY				(WREADY),
	//写响应通道                
	.BID				(BID),
	.BRESP				(BRESP),
//	output reg [USER_WIDTH-1:0]	BUSER,
	.BVALID				(BVALID),
	.BREADY				(BREADY),
	/********** 输出信号 **********/
	.wen				(wen),
	.awsize				(awsize),
	.awaddr				(awaddr),
	.wdata				(wdata)
	);

    //=========================================================
    //读通道例化
	axi_r_channel#(
		.DATA_WIDTH(DATA_WIDTH),
		.ADDR_WIDTH(ADDR_WIDTH),
		.ID_WIDTH(ID_WIDTH),
		.USER_WIDTH(USER_WIDTH),
		.STRB_WIDTH(DATA_WIDTH/8)
	)u_axi_r_channel(
		 /********* 时钟&复位 *********/
	.ACLK				(ACLK),
	.ARESETn			(ARESETn),
	/******** AXI总线信号 ********/
	//读地址地址                
	.ARID				(ARID),
	.ARADDR				(ARADDR),
	.ARLEN				(ARLEN),
	.ARSIZE				(ARSIZE),
	.ARBURST			(ARBURST),
//	input	  	                ARLOCK,
//	input	   [3:0]	        ARCACHE,
//	input	   [2:0]            ARPROT,
//	input	   [3:0]	        ARQOS,
//	input	   [3:0]	        ARREGION,
//	input	   [USER_WIDTH-1:0]	ARUSER,
	.ARVALID			(ARVALID),
	.ARREADY			(ARREADY),
	//读数据通道                
	.RID				(RID),
	.RDATA				(RDATA),
	.RRESP				(RRESP),
	.RLAST				(RLAST),
//	output reg [USER_WIDTH-1:0] RUSER,
	.RVALID				(RVALID),
	.RREADY				(RREADY),
	/********** 输入信号 **********/
    .sram_rdata			(sram_rdata),
	/********** 输出信号 **********/
	.ren				(ren),
	.arsize				(arsize),
	.araddr				(araddr)
	);



endmodule